The term EPROM stands for electrically programmable read-only memory. In contrast to a random access memory (RAM), an EPROM comprises a memory which retains information even if the power supply to the memory is switched off. The EPROM device comprises a field effect transistor having a source, a drain and a conduction channel between the source and drain. Additionally, the field effect transistor has a gate floating above the channel. The floating gate is electrically isolated. Information is stored by injecting charges on the floating gate. Due to its isolation, the charges remain on the floating gate, even if the power supply is switched off. The charges on the floating gate effect the conductance of the channel between the source and the drain of the field effect transistor. The information may be retrieved from the memory device by measuring the current flowing between the source and the drain.
A schematic depiction of a more advanced EPROM device, called single-poly EPROM device, is given in FIGS. 1 and 2. FIG. 1 shows a top view of the single-poly EPROM device. The single-poly EPROM device of FIG. 1 comprises a floating gate 10, a control gate 12, a source 16 and a drain 18. Source 16, drain 18 and floating gate 10 form a field effect transistor (usually called a “read transistor”), wherein the floating gate 10 represents the gate of the field effect transistor. The channel between source 16 and drain 18 is covered by part of the floating gate 10 in FIG. 1. A back gate contact 14b, a drain contact 14D, and a source contact 14S are respectively connected to a back gate 20, the source 18 and the drain 16. A peculiarity of the illustrated single-poly EPROM device is that the control gate 12 is not formed by a conductive layer on top of the floating gate 10, but by a doped semiconductor region underlying part of the floating gate 10. The floating gate 10 is made out of a polysilicon (“poly”) layer on top of both the channel of the field effect transistor and the control gate 12. Two control gate contacts 14C are connected to the control gate 12 (although a simple control gate is sufficient for functionality).
FIG. 2 shows a schematic cross section of the single-poly EPROM device of FIG. 1. The floating gate 10 is situated above both the control gate 12 and the channel between source 16 and drain 18. The back gate 20 shown in FIG. 2 has the same purpose as in standard MOS transistors. Reference numeral C1 depicts the capacitance between the floating gate 10 and the control gate 12 of the single-poly EPROM device shown in FIG. 2. Single-poly EPROM devices can be programmed either through hot carrier injection or Fowler-Nordheim tunneling. A thin gate oxide is provided as insulator between the floating gate 10 and the channel region. The channel region can be used for tunneling between the floating gate 10 and source 16/drain 18.
In a conventional single-poly EPROM, the floating gate 10 is controlled by a large (n−) well diffusion which is placed under a large area fraction of the floating poly, i.e., the control gate 12 of FIG. 1. This area has to be large, because the coupling ratio is approximately given by the overlap area divided by the read transistor active area. Therefore, single-poly EPROM cells usually cover a large silicon area, which is 5 to 20 times larger than double poly EPROMs.